In the storage and retrieval of digital information, whether computer digital data or digitized representations of video or audio or other signals, different media have been utilized. In prior art storage and retrieval of digitized video or other data at real time rates, static RAMs (SRAMs) have been predominantly used, primarily due to ease of interface with other components and subsystems within the system. SRAMs are generally easier to use for high speed video and data storage, have fewer special modes and signal requirements, and don't require refreshing. However, SRAMs use more transistors per bit of storage. Thus for a given amount of storage they are substantially more expensive in cost, space and power usage.
On the other hand, Dynamic Random Access Memory (DRAM) is the most efficient semiconductor memory available in terms of cost, size and power. However, there are several attendant drawbacks to the use of DRAM, for example, the timing signals required to drive it are complex and very specific to the DRAM type and mode used; DRAM must be refreshed at regular times to retain data; and access time depends on the particular sequence of Row and Column Addresses applied to the DRAM. In some instances, the designer must typically add a complex state machine to the system to generate the required timing. In addition, the user data flow must be interrupted to allow time for refresh of the memory system.
In accordance with an aspect of the present invention, there is provided a cost effective Dynamic Random Access Memory (DRAM) controller system to enable the use of lower cost DRAMs in applications previously utilizing SRAMs.
The present invention obviates many of the disadvantages of the prior art and provides further related advantages.